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W9751G6IB
7.2.4
On-Die Termination (ODT)
On-Die Termination (ODT) is a new feature on DDR2 components that allows a DRAM to turn on/off
termination resistance for each DQ, UDQS/ UDQS , LDQS/ LDQS , UDM and LDM signal via the ODT
control pin. UDQS and LDQS are terminated only when enabled in the EMR (1) by address bit A10 =
0. The ODT feature is designed to improve signal integrity of the memory channel by allowing the
DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT function can be used for all active and standby modes. ODT is turned off and not supported
in Self Refresh mode. (Example timing waveforms refer to 10.3, 10.4 ODT Timing for
Active/Standby/Power Down Mode and 10.5, 10.6 ODT timing mode switch at entering/exiting power
down mode diagram in Chapter 10)
DRAM
Input
Buffer
V DDQ
sw1
Rval1
Rval1
sw1
V SSQ
V DDQ
sw2
Rval2
Rval2
sw2
V SSQ
V DDQ
sw3
Rval3
Rval3
sw3
V SSQ
Input
Pin
Switch (sw1, sw2, sw3) is enabled by ODT pin.
Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR (1).
Termination included on all DQs, DM, DQS, DQS pins.
Figure 9 — Functional Representation of ODT
7.2.5
ODT related timings
7.2.5.1 MRS command to ODT update delay
During normal operation the value of the effective termination resistance can be changed with an
EMRS command. The update of the Rtt setting is done between t MOD ,min and t MOD ,max, and CKE
must remain HIGH for the entire duration of t MOD window for proper operation. The timings are shown
in the following timing diagram.
Publication Release Date: Oct. 23, 2009
- 18 -
Revision A06
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